The fabrication of semiconductor integrated circuits requires an increasingly expensive and integrated set of tightly controlled processes to obtain the desired critical dimensions (CD) of the physical integrated circuit features within acceptable product yield. This is particularly true with respect to the control of the etching of metal lines within the integrated circuit structure.
Current metal etch tool performance monitoring uses a standard set of recipes. FIG. 1 provides a flow chart of the conventional control process. As shown in FIG. 1, the process begins at step 102 with an initial measurement of photoresist mask width at the base of the pattern to determine whether the wafer lot passes the DICD test. If the lot passes DICD, then the DICD data is sent to the wafer fabrication data collection system. Next, at step 104, the wafer lot is loaded on the etcher and, at step 106, the wafer lot is etched according to a standard etch recipe typically used for this particular metal layer in the device design. The etch end point time and the RF counter for the etch tool, i.e., the “age” of the tool, are recorded in a file and a file name is given to the wafer lot. Then, at step 108, the wafer lot is cleaned with a solvent to remove etch process by-products. Finally, the wafer lot is measured for FICD's, the FICD's are recorded in the lot file and a bias, based upon the difference between the FICD and the DICD for the lot, is calculated and used as a monitor of tool performance.
This conventional method of control suffers from the disadvantages that every wafer lot etches somewhat differently and etch tool performance changes with time.